1) The power consumption of static CMOS gates varies with the _____ of power supply voltage.
a. square
b. cube
c. fourth power
d. 1/8 th power
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Answer
Explanation
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ANSWER: square
Explanation:
No explanation is available for this question!
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2) In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count?
a. Input pad design
b. Output pad design
c. Three state pad design
d. All of the above
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Answer
Explanation
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ANSWER: Three state pad design
Explanation:
No explanation is available for this question!
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3) Maze routing is used to determine the _______path for a single wire between a set of points, if any path exists.
a. Shortest
b. Average
c. Longest
d. None of the above
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Answer
Explanation
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ANSWER: Shortest
Explanation:
No explanation is available for this question!
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4) Maze routing is also known as ________
a. Viterbi's algorithm
b. Lee/Moore algorithm
c. Prim's algorithm
d. Quine-McCluskey algorithm
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Answer
Explanation
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ANSWER: Lee/Moore algorithm
Explanation:
No explanation is available for this question!
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5) In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density?
a. Placement
b. Global Routing
c. Detailed Routing
d. All of the above
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Answer
Explanation
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ANSWER: Placement
Explanation:
No explanation is available for this question!
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6) In floorplanning, placement and routing are __________ tools.
a. Front end
b. Back end
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Back end
Explanation:
No explanation is available for this question!
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7) In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and other interconnection discontinuities?
a. Power/Ground Noise
b. Crosstalk Noise
c. Reflection Noise
d. All of the above
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Answer
Explanation
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ANSWER: Reflection Noise
Explanation:
No explanation is available for this question!
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8) Increase in the physical distance of H-tree _________the skew rate.
a. Increases
b. Stabilizes
c. Decreases
d. All of the above
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Answer
Explanation
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ANSWER: Increases
Explanation:
No explanation is available for this question!
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9) Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points?
a. H tree
b. Balanced tree clock network
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: H tree
Explanation:
No explanation is available for this question!
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10) Before the commencement of design, the clocking strategy determine/s __________
a. Number of clock signals necessary for routing throughout the chip
b. Number of transistors used per storage requirement
c. Power dissipated by chip & the size of chip
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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